The present invention relates generally to the field of data transfer technology. More specifically, the present invention relates to an apparatus, method, and system for host-based validation of data transferred between a storage device and a host.
As computer devices and systems continue to advance and become more complex, effective and efficient techniques for transferring data between various components in computer systems have become more and more critical in system design and implementation. In particular, data transfer between an I/O device (e.g., a hard disk) and a host device (e.g., system memory) has been constantly examined and improved in order to improve the system""s total performance and reliability. In the PC industry, the performance of the hard disk drive, which is the central I/O device of the PC, has become more and more important due to continual performance increases in the CPU, system memory and other various components of the PC.
The hard drive interface in a PC system provides the path for transferring data between a hard drive and system memory. The vast majority of PC systems today rely on the Advanced Technology Attachment (ATA), also referred to as the Integrated Drive Electronics (IDE), hard disk drive interface to transfer data between the hard disk and the system memory. Various data transfer protocols or standards have been developed to facilitate and control the various aspects of data transfer through an ATA/IDE interface. Data transfer protocols or standards such as the programmed input/output (PIO) and direct memory access (DMA) modes were developed to take advantage of the local bus architectures that replaced the original ISA bus. ATA interface modes have improved from PIO to DMA and now Ultra DMA, with data transfer rates up to 33.3 Mbytes/sec and 66.6 Mbytes/sec according to the Ultra ATA/33 and the Ultra ATA/66 protocols, respectively.
ATA-4 includes Ultra ATA/33 which uses both the rising and falling edges of the strobe signal as signal separators. Using both edges of the strobe signal effectively allows the available transition frequency to be doubled without increasing the frequency of the strobe, thus doubling the burst transfer rate. ATA-5 includes Ultra ATA/66 which doubles the Ultra ATA burst transfer rate by reducing setup times and increasing the strobe rate.
Currently, the existing ATA or DMA data transfer protocols only allows for validation of the data transferred between a device and a host to be performed by the device, not the host. Conventionally, the device is responsible for determining whether data has been transferred correctly at the end of a command (e.g., a read command) by comparing a cyclic redundancy code (CRC) value calculated by the host with a CRC value calculated by the device with respect to the data transferred. If the CRC values do not match, the device will set an error flag in its status register to indicate an error condition with respect to the data transferred. A software device driver or service routine on the host side can check the error flag in the status register of the device to determine if a CRC error has occurred with respect to the data transferred from the device. Since a read command can be very long, it is not efficient for the host to wait for the entire transfer to be completed before knowing from the device""s status information whether the transfer is successful. This problem is significant considering that a disk read request issued by the host typically contains a demand portion (usually for a small amount of data) and a pre-fetch portion (usually for a large amount of data). In this instance, the transfer of the demand portion will have completed long before the entire transfer (including the transfer of the pre-fetch portion) is completed. Currently, there is no mechanism according to the existing ATA or DMA data transfer protocols for the host side to determine at some intermediate point (e.g., at the point when the demand portion is completed) if the data already received from the device was correctly transferred or not. Since the pre-fetched data is speculative, in order to avoid incurring a performance penalty, the host should not have to wait for the completion of the pre-fetch data before it can proceed to use the demand-fetched data. In addition, as the pre-fetch length is long and the CPU power continues to increase, it is increasing likely that a request for subsequent data (i.e., a pre-fetch hit) will be submitted by the host while the pre-fetch transfer is still in progress. Since most transfer lengths initiated by the host are typically small, the transfer of subsequent requested data which is a pre-fetch hit would have been completed before the entire pre-fetch request is completed. The host should not have to wait for the entire transfer to complete before allowed to proceed with the portion of the data transfer which is pre-fetch hit. Similarly, when a request is issued which is not a pre-fetch hit, the host should not have to wait for the entire pre-fetch transfer to complete before it can abort the pre-fetch request in progress and proceed with servicing the new request.
According to one aspect of the present invention, a method is provided in which a device, in response to a read request issued by a host, transfers data to the host through a series of direct memory access (DMA) data in bursts. The host is allowed to interrupt the read command and determine whether a first portion has been transferred correctly from the device based upon an error code calculation transmitted from the device to the host during the termination phase of a data in burst.